Developments in integrated circuit technology have often focused on improving the integration density of various electronic components (e.g. transistors, capacitors, diodes, resistors, inductors, or the like) into a given chip or wafer area. Various improvements have reduced component sizes, permitting more components to be integrated on the surface of the semiconductor die. Such two-dimensional (2D) integration density improvements are physically limited by device size, the size of the die, and other limitations including the complexity of design.
IC packaging has evolved, such that multiple ICs may be vertically stacked in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). Some 3D IC packages include the use of through substrate vias (TSV), also referred to as through-silicon-vias, in the case of silicon-based dies. The inclusion of TSV increases the complexity of semiconductor fabrication and packaging. For example, TSV-to-TSV coupling is an additional noise source for 3D IC packages.
Another form of 3D IC integrates the fabrication process in two or more stacked tiers. Each tier has a semiconductor or dielectric layer and an interconnect structure. If an upper tier includes active devices, that upper tier has a thin semiconductor substrate or layer over the interconnect structure of the adjacent lower tier. An upper tier interconnect structure connects the devices in the upper tier to one another and to external pins. Inter-tier vias (also referred to as inter-level vias, ILV) provide additional connections between lower tier devices and upper tier devices.